The present invention relates in general to the formation of metal silicide interconnects, and, more particularly, to a process of forming a metal silicide interconnects using a layer of amorphous silicon.
In the manufacture of integrated circuits used in the construction of dynamic random access memories (DRAMs), static random access memories (SRAMs), and the like, interconnects are required to provide the necessary electrical paths between field effect transistors and other devices fabricated on the semiconductor substrate and the external circuitry used to pass data to and from these devices. Heavily-doped polysilicon is commonly used to form the gate as well as the drain/source contacts of a metal oxide semiconductor field effect transistor (MOSFET) because of its compatibility with the underlying silicon semiconductor structure. Titanium silicide (TiSi.sub.2) is commonly used in conjunction with the polysilicon to form the necessary interconnects as it is compatible with the polysilicon and, more importantly, reduces the sheet resistance of the polysilicon. Polycide contacts and interconnects comprising polysilicon and titanium silicide are increasingly being used with MOSFETs having self-aligned gates.
TiSi.sub.2 typically exists in two phases, C49 and C54. The C49 phase of TiSi.sub.2 occurs when a layer of TiSi.sub.2 is first formed. The C49 phase is then annealed at a sufficient temperature to convert the higher resistivity phase C49 TiSi.sub.2 (smaller grain size) to the lower resistivity phase C54 TiSi.sub.2 (larger grain size). As TiSi.sub.2 is used to lower the resistance of polysilicon, it is desirable to convert C49 TiSi.sub.2 to C54 TiSi.sub.2. It is well known that the TiSi.sub.2 salicide process is only scalable to a gate length which is larger than the C49 grain size. For gate lengths which are less than the C49 grain size, the thermal budget required to transform the C49 phase to the desired C54 phase increases dramatically, leading to agglomeration and formation of Kirkendall voids.
While agglomeration of TiSi.sub.2 can be suppressed by high temperature sputtering of Ti, the sheet resistance (Rs) of the TiSi.sub.2 still degrades due to Kirkendall void formation in gate lines with a width of 0.1 .mu.m or less. The voids can be effectively suppressed by thinning the deposited Ti film as thin Ti film is easier to bend. However, thinner Ti film further degrades Rs because the silicide formation is surpassed by the nitride formation during the N.sub.2 anneal. It is therefore desirable to enhance the silicidation process by limiting the consumption of silicon from the polysilicon during the formation of TiSi.sub.21 while also reducing the nitridation of Ti.
Typically, TiSi.sub.2 is formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD). PVD entails sputtering titanium onto the semiconductor structure, and particularly, onto the polysilicon. TiSi.sub.2 is then formed by annealing the structure at the appropriate temperature and for an appropriate period of time. However, the anneal consumes part of silicon in the polysilicon in forming the TiSi.sub.2, thereby degrading the silicidation process and increasing the formation of voids. In CVD, titanium tetrachloride (TiCl.sub.4) is combined with silane (SiH.sub.4) in the gas phase at an appropriate temperature to form TiSi.sub.2 and HCl. However, silicon from the underlying layer of polysilicon is also partially consumed in this reaction.
A number of techniques have been devised to reduce the consumption of the underlying polysilicon in forming TiSi.sub.2. One such method includes pre-amorphization of the underlying polysilicon by ion implantation. However, such a method is expensive and requires complex steps in controlling the thickness and doping level of the polysilicon. Another method is disclosed in U.S. Pat. No. 5,173,450 to Wei in which a layer of polysilicon is formed over a semiconductor structure, followed by a layer of titanium and a layer of amorphous silicon. The layer of amorphous silicon is formed over the layer of titanium in order to provide a source of silicon for the formation of the TiSi.sub.2. However, the reaction also consumes silicon from the polysilicon with the requisite degradation of the silicidation process and increased void formation.
Accordingly, there is a need for a method of forming a metal silicide interconnect in which the silicidation process is enhanced by limiting the consumption of silicon from the polysilicon during the formation of the metal silicide and by also reducing the nitridation of the metal. Preferably, such a method could be used in forming a sub 0.1 .mu.m gate structure, would be inexpensive, easy to implement, and would not entail excess processing steps.